This document describes a simulated machine that we will be using in this course. The simulated machine is primarily based upon a 1946 report by Burks, Goldstine and Von Neumann of the Institute for Advanced Studies (IAS) in Princeton, New Jersey. The I/O instructions are based upon an April 1953 article by Estrin describing the actual machine that was built. However, the simulated machine differs from the 1946 design and the actual machine in numerous ways. Some differences exist because I did not have full documentation (e.g. exactly how were instructions encoded?) and some differences exist to simplify the machine for a modern audience (e.g. the actual machine did fixed point calculations, not two's complement integer calculations).
The IAS computer has 4096 40-bits words of memory.
The machine has the following registers:
The machine is a two's complement machine. It only supports integer types.
The machine is a "one-address" machine, which means that most instructions operate on the accumulator and one memory location.
Instructions are 20 bits long. Therefore two instructions are packed in one memory location. The instruction in the low-order bits will execute first when execution reaches a particular word of memory. In effect, the PC is augmented with a flag (called offsetPC) that tracks which instruction in the word pointed to by the PC will execute next. (If offsetPC is 0, then the low-order instruction is next. If offsetPC is 1, then the high-order instruction is next.)
An instruction consists of three components:
The following table describes the IAS instruction set. In the table X refers to the contents of the instruction's address field. In the INCARD and OUTCARD instructions, n is the value in the MQ register. Some of the instructions (MUL, LSHIFT and RSHIFT) treat the AC and MQ registers as a single 80-bit unit. In these cases AC contains the upper 40 bits and MQ contains the lower 40 bits.
| Opcode | Encoding | Opcode 2 | Encoding 2 | Description |
| LOAD | 0x01 | LDABS | 0x0 | AC <- |Mem(X)| |
| LOAD | 0x01 | LDNEGABS | 0x1 | AC <- -|Mem(X)| |
| LOAD | 0x01 | LD | 0x2 | AC <- Mem(X) |
| LOAD | 0x01 | LDNEG | 0x3 | AC <- -Mem(X) |
| LOAD | 0x01 | ADDABS | 0x4 | AC <- AC + |Mem(X)| |
| LOAD | 0x01 | SUBABS | 0x5 | AC <- AC - |Mem(X)| |
| LOAD | 0x01 | ADD | 0x6 | AC <- AC + Mem(X) |
| LOAD | 0x01 | SUB | 0x7 | AC <- AC - Mem(X) |
| MUL | 0x02 | AC,MQ <- AC * Mem(X) | ||
| DIV | 0x03 | AC <- AC / Mem(X); MQ <- AC % Mem(X) | ||
| LDMQ | 0x04 | MQ <- Mem(X) | ||
| LSHIFT | 0x05 | AC,MQ <- AC,MQ << X (fills with zeros) | ||
| RSHIFT | 0x06 | AC,MQ <- AC,MQ >> X (replicates the sign) | ||
| ST | 0x07 | Mem(X) <- AC | ||
| UBL | 0x08 | PC <- X; offsetPC <- 0 | ||
| UBH | 0x09 | PC <- X; offsetPC <- 1 | ||
| CBL | 0x0A | if AC >= 0 then PC <- X; offsetPC <- 0 | ||
| CBH | 0x0B | if AC >= 0 then PC <- X; offsetPC <- 1 | ||
| MOVE | 0x0C | MVABS | 0x0 | AC <- |MQ| |
| MOVE | 0x0C | MVNEGABS | 0x1 | AC <- -|MQ| |
| MOVE | 0x0C | MV | 0x2 | AC <- MQ |
| MOVE | 0x0C | MVNEG | 0x3 | AC <- -MQ |
| MOVE | 0x0C | ADDMQABS | 0x4 | AC <- AC + |MQ| |
| MOVE | 0x0C | SUBMQABS | 0x5 | AC <- AC - |MQ| |
| MOVE | 0x0C | ADDMQ | 0x6 | AC <- AC + MQ |
| MOVE | 0x0C | SUBMQ | 0x7 | AC <- AC - MQ |
| AMODL | 0x0D | Mem(X)[bits 0:11] <- AC[bits 0:11] | ||
| AMODH | 0x0E | Mem(X)[bits 20:31] <- AC[bits 0:11] | ||
| IO | 0x0F | INCARD | 0x0 | Mem(X:X+((n*12)-1)) <- read n cards |
| IO | 0x0F | OUTCARD | 0x1 | write n cards <- Mem(X:X+((n*12)-1)) |
Comments and questions should be directed to hatcher@unh.edu